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| LT3800 High-Voltage Synchronous Current Mode Step-Down Controller DESCRIPTIO The LT(R)3800 is a 200kHz fixed frequency high voltage synchronous current mode step-down switching regulator controller. The IC drives standard gate N-channel power MOSFETs and can operate with input voltages from 4V to 60V. An onboard regulator provides IC power directly from VIN and provides for output-derived power to minimize VIN quiescent current. MOSFET drivers employ an internal dynamic bootstrap feature, maximizing gate-source "ON" voltages during normal operation for improved operating efficiencies. The LT3800 incorporates Burst Mode(R) operation, which reduces no load quiescent current to under 100A. Light load efficiencies are also improved through a reverse inductor current inhibit, allowing the controller to support discontinuous operation. Both Burst Mode operation and the reverse-current inhibit features can be disabled if desired. The LT3800 incorporates a programmable soft-start that directly controls the voltage slew rate of the converter output for reduced startup surge currents and overshoot errors. The LT3800 is available in a 16-lead thermally enhanced TSSOP package. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 6611131, 6304066, 6498466, 6580258. FEATURES Wide 4V to 60V Input Voltage Range Output Voltages up to 36V Adaptive Nonoverlap Circuitry Prevents Switch Shoot-Through Reverse Inductor Current Inhibit for Discontinuous Operation Improves Efficiency with Light Loads Output Slew Rate Controlled Soft-Start with Auto-Reset 100A No Load Quiescent Current Low 10A Current Shutdown 1% Regulation Accuracy 200kHz Operating Frequency Standard Gate N-Channel Power MOSFETs Current Limit Unaffected by Duty Cycle Reverse Overcurrent Protection 16-Lead Thermally Enhanced TSSOP Package APPLICATIO S 12V and 42V Automotive and Heavy Equipment 48V Telecom Power Supplies Avionics and Industrial Control Systems Distributed Power Converters TYPICAL APPLICATIO VIN 20V TO 55V 12V 75W DC/DC Converter with Reverse Current Inhibit and Input UVLO + 56F x2 1M 82.5k 1.5nF SHDN 200k CSS 20k 1% 174k 1% BURST_EN VFB VC 100pF 82.5k 680pF SENSE- VCC 1F BG PGND SENSE+ SGND Si7370DP B160 1N4148 LT3800 SW BAS19 15H 1F x3 1F TG Si7850DP 95 90 85 80 LOSS (48V) 75 70 0.1 1 0 VIN = 36V VIN = 60V VIN = 48V 100 VIN = 24V 5 VIN BOOST EFFICIENCY (%) 0.015 + 10F VOUT 12V AT 75W 270F 3800 TA01a U U U Efficiency and Power Loss 6 POWER LOSS (W) 4 3 2 1 ILOAD (A) 10 3800 TA01b 3800fb 1 LT3800 ABSOLUTE AXI U RATI GS (Note 1) PI CO FIGURATIO TOP VIEW VIN NC SHDN CSS BURST_EN VFB VC SENSE - Supply Voltages Input Supply Pin (VIN) .............................. -0.3V to 65V Boosted Supply Pin (BOOST) ................... -0.3V to 80V Boosted Supply Voltage (BOOST - SW) .. -0.3V to 24V Boosted Supply Reference Pin (SW) ........... -2V to 65V Local Supply Pin (VCC) ............................. -0.3V to 24V Input Voltages SENSE+, SENSE- ...................................... -0.3V to 40V SENSE+ - SENSE- ......................................... -1V to 1V BURST_EN Pin ......................................... -0.3V to 24V Other Inputs (SHDN, CSS, VFB, VC) .......... -0.3V to 5.0V Input Currents SHDN, CSS ............................................... -1mA to 1mA Maximum Temperatures Operating Junction Temperature Range (Note 2) LT3800E (Note 3) ............................. -40C to 125C LT3800I ............................................ -40C to 125C Storage Temperature Range ................. -65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C 1 2 3 4 5 6 7 8 17 16 BOOST 15 TG 14 SW 13 NC 12 VCC 11 BG 10 PGND 9 SENSE+ FE PACKAGE 16-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 40C/W, JC = 10C/W EXPOSED PAD (PIN 17) IS SGND MUST BE SOLDERED TO PCB ORDER I FOR ATIO LEAD FREE FINISH LT3800EFE#PBF LT3800IFE#PBF TAPE AND REEL LT3800EFE#TRPBF LT3800IFE#TRPBF PART MARKING 3800EFE 3800IFE PACKAGE DESCRIPTION 16-Lead Plastic TSSOP 16-Lead Plastic TSSOP Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V, SENSE - = SENSE+ = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted. SYMBOL VIN PARAMETER Operating Voltage Range (Note 4) Minimum Start Voltage UVLO Threshold (Falling) UVLO Hysteresis VIN Supply Current VIN Burst Mode Current VIN Shutdown Current Operating Voltage Operating Voltage Range (Note 5) UVLO Threshold (Rising) UVLO Hysteresis VCC > 9V VBURST_EN = 0V, VFB = 1.35V VSHDN = 0V VBOOST - VSW VBOOST - VSW VBOOST - VSW CONDITIONS ELECTRICAL CHARACTERISTICS MIN 4 7.5 3.65 IVIN VBOOST 2 U TEMPERATURE RANGE -40C to 125C -40C to 125C TYP MAX 60 3.80 670 20 20 8 3.95 UNITS V V V mV A A A V V V V 3800fb U U U U WW W W U 15 75 20 5 0.4 LT3800 The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VIN = 20V, VCC = BOOST = BURST_EN = 10V, SHDN = 2V, SENSE - = SENSE+ = 10V, SGND = PGND = SW = 0V, CTG = CBG = 3300pF, unless otherwise noted. SYMBOL IBOOST PARAMETER BOOST Supply Current (Note 6) BOOST Burst Mode Current BOOST Shutdown Current Operating Voltage (Note 5) Output Voltage UVLO Threshold (Rising) UVLO Hysteresis VCC Supply Current (Note 6) VCC Burst Mode Current VCC Shutdown Current Short-Circuit Current Enable Threshold (Rising) Threshold Hysteresis Common Mode Range Current Limit Sense Voltage Reverse Protect Sense Voltage Reverse Current Offset Input Current (ISENSE+ + ISENSE-) Operating Frequency ELECTRICAL CHARACTERISTICS CONDITIONS VBURST_EN = 0V VSHDN = 0V MIN TYP 1.4 0.1 0.1 8.0 6.25 500 3 80 20 -120 1.35 120 150 -150 10 0.8 -20 -0.3 MAX UNITS mA A A VCC 20 8.3 V V V mV mA A A mA V mV mV mV mV mA A mA IVCC 3.6 VBURST_EN = 0V VSHDN = 0V -40 1.30 0 140 VSHDN VSENSE 1.40 36 175 VSENSE+ - VSENSE- VSENSE+ - VSENSE-, VBURST_EN = VCC VBURST_EN = 0V or VBURST_EN = VFB VSENSE(CM) = 0V VSENSE(CM) = 2.75V VSENSE(CM) > 4V ISENSE fO VFB IFB VFB(SS) ICSS gm AV VC IVC VTG,BG tTG,BG tTG(OFF) tTG(ON) tNOL 190 175 1.224 1.215 200 1.231 25 210 220 1.238 1.245 kHz kHz V V nA V mV A Error Amp Reference Voltage Feedback Input Current Soft-Start Disable Voltage Soft-Start Disable Hysteresis Soft-Start Capacitor Control Current Error Amp Transconductance Error Amp DC Voltage Gain Error Amp Output Range Error Amp Sink/Source Current Gate Drive Output On Voltage (Note 7) Gate Drive Output Off Voltage Gate Drive Rise/Fall Time Minimum Off Time Minimum On Time Gate Drive Nonoverlap Time Measured at VFB Pin VFB Rising 1.185 300 2 275 350 62 1.2 30 9.8 0.1 400 mhos dB V A V V ns ns Zero Current to Current Limit 10% to 90% or 90% to 10% 50 450 300 200 150 500 ns ns ns TG Fall to BG Rise BG Fall to TG Rise 3800fb 3 LT3800 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: The LT3800E is guaranteed to meet performance specifications from 0C to 125C junction temperature. Specifications over the -40C to 125C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The LT3800I is guaranteed over the full -40C to 125C operating junction temperature range. Note 4: VIN voltages below the start-up threshold (7.5V) are only supported when VCC is externally driven above 6.5V. Note 5: Operating range dictated by MOSFET absolute maximum gatesource voltage ratings. Note 6: Supply current specification does not include switch drive currents. Actual supply currents will be higher. Note 7: DC measurement of gate drive output "ON" voltage is typically 8.6V. Internal dynamic bootstrap operation yields typical gate "ON" voltages of 9.8V during standard switching operation. Standard operation gate "ON" voltage is not tested but guaranteed by design. TYPICAL PERFOR A CE CHARACTERISTICS Shutdown Threshold (Rising) vs Temperature 1.37 SHUTDOWN THRESHOLD, FALLING (V) SHUTDOWN THRESHOLD, RISING (V) 1.36 1.35 1.230 VCC (V) 1.34 1.33 -50 -25 0 25 50 75 TEMPERATURE (C) VCC vs ICC(LOAD) 8.05 8 TA = 25C 7 8.00 6 ICC CURRENT LIMIT (mA) VCC (V) VCC (V) 7.95 7.90 7.85 0 5 10 15 20 25 ICC(LOAD) (mA) 30 4 UW 100 3800 G01 Shutdown Threshold (Falling) vs Temperature 1.240 VCC vs Temperature 8.1 1.235 ICC = 0mA 8.0 ICC = 20mA 7.9 1.225 125 1.220 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 7.8 -50 -25 0 50 75 25 TEMPERATURE (C) 100 125 3800 G02 3800 G03 VCC vs VIN ICC = 20mA TA = 25C ICC Current Limit vs Temperature 200 175 150 125 100 75 50 -50 5 4 3 35 40 4 5 6 7 8 VIN (V) 3800 G04 3800 G05 9 10 11 12 -25 0 25 50 75 TEMPERATURE (C) 100 125 3800 G06 3800fb LT3800 TYPICAL PERFOR A CE CHARACTERISTICS VCC UVLO Threshold (Rising) vs Temperature 6.30 25 20 6.25 ERROR AMP TRANSCONDUCTANCE (mho) VCC UVLO THRESHOLD, RISING (V) ICC (A) 6.20 5 6.15 -50 -25 0 25 50 75 TEMPERATURE (C) I(SENSE+ + SENSE-) vs VSENSE(CM) 800 600 I(SENSE+ + SENSE-) (A) OPERATING FREQUENCY (kHz) 210 400 200 0 -200 -400 ERROR AMP REFERENCE (V) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VSENSE(CM) (V) 3800 G09 PI FU CTIO S VIN (Pin 1): Converter Input Supply. NC (Pin 2): No Connection. SHDN (Pin 3): Precision Shutdown Pin. Enable threshold is 1.35V (rising) with 120mV of input hysteresis. When in shutdown mode, all internal IC functions are disabled. The precision threshold allows use of the SHDN pin to incorporate UVLO functions. If the SHDN pin is pulled below 0.7V, the IC enters a low current shutdown mode with IVIN < 10A. In low-current shutdown, the IC will sink 20A from the VCC pin until that local supply has collapsed. Typical pin input bias current is <10nA and the pin is internally clamped to 6V. CSS (Pin 4): Soft-Start AC Coupling Capacitor Input. Connect capacitor (CSS) in series with a 200k resistor from pin to converter output (VOUT). Controls converter startup output voltage slew rate (VOUT/t). Slew rate corresponds to 2A average current through the soft-start coupling capacitor. The capacitor value for a desired output startup slew rate follows the relation: CSS = 2A/(VOUT/t) Shorting this pin to SGND disables the soft-start function BURST_EN (Pin 5): Burst Mode Operation Enable Pin. This pin also controls reverse-inhibit mode of operation. When the pin voltage is below 0.5V, Burst Mode operation 3800fb UW 100 3800 G07 ICC vs VCC (SHDN = 0V) TA = 25C Error Amp Transconductance vs Temperature 380 360 15 10 340 125 0 0 2 4 6 8 10 12 14 16 18 20 VCC (V) 3800 G12 320 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 3800 G08 Operating Frequency vs Temperature 220 Error Amp Reference vs Temperature 1.232 TA = 25C 1.231 1.230 200 1.229 190 1.228 180 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 1.227 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 3800 G10 3800 G11 U U U 5 LT3800 PI FU CTIO S and reverse-current inhibit functions are enabled. When the pin voltage is above 0.5V, Burst Mode operation is disabled, but reverse-current inhibit operation is maintained. DC/DC converters operating with reverse-current inhibit operation (BURST_EN = VFB) have a 1mA minimum load requirement. Reverse-current inhibit is disabled when the pin voltage is above 2.5V. This pin is typically shorted to ground to enable Burst Mode operation and reversecurrent inhibit, shorted to VFB to disable Burst Mode operation while enabling reverse-current inhibit, and connected to VCC pin to disable both functions. See Applications Information section. V FB (Pin 6): Error Amplifier Inverting Input. The noninverting input of the error amplifier is connected to an internal 1.231V reference. Desired converter output voltage (VOUT) is programmed by connecting a resistive divider from the converter output to the VFB pin. Values for the resistor connected from VOUT to VFB (R2) and the resistor connected from VFB to ground (R1) can be calculated via the following relationship: V R2 = R1 * OUT - 1 1.231 The VFB pin input bias current is 25nA, so use of extremely high value feedback resistors could cause a converter output that is slightly higher than expected. Bias current error at the output can be estimated as: VOUT(BIAS) = 25nA * R2 VC (Pin 7): Error Amplifier Output. The voltage on the VC pin corresponds to the maximum (peak) switch current per oscillator cycle. The error amplifier is typically configured as an integrator by connecting an RC network from this pin to ground. This network creates the dominant pole for the converter voltage regulation feedback loop. Specific integrator characteristics can be configured to optimize transient response. Connecting a 100pF or greater high frequency bypass capacitor from this pin to ground is also recommended. When Burst Mode operation is enabled (see Pin 5 description), an internal low impedance clamp on the VC pin is set at 100mV below the burst threshold, which limits the negative excursion of the pin voltage. Therefore, this pin cannot be pulled low with a low-impedance source. If the VC pin must be externally manipulated, do so through a 1k series resistance. SENSE- (Pin 8): Negative Input for Current Sense Amplifier. Sensed inductor current limit set at 150mV across SENSE inputs. SENSE+ (Pin 9): Positive Input for Current Sense Amplifier. Sensed inductor current limit set at 150mV across SENSE inputs. PGND (Pin 10): High Current Ground Reference for Synchronous Switch. Current path from pin to negative terminal of VCC decoupling capacitor must not corrupt SGND. BG (Pin 11): Synchronous Switch Gate Drive Output. VCC (Pin 12): Internal Regulator Output. Most IC functions are powered from this pin. Driving this pin from an external source reduces VIN pin current to 20A. This pin is decoupled with a low ESR 1F capacitor to PGND. In shutdown mode, this pin sinks 20A until the pin voltage is discharged to 0V. See Typical Performance Characteristics. NC (Pin 13): No Connection. SW (Pin 14): Reference for VBOOST Supply and High Current Return for Bootstrapped Switch. TG (Pin 15): Bootstrapped Switch Gate Drive Output. BOOST (Pin 16): Bootstrapped Supply - Maximum Operating Voltage (Ground Referred) to 75V. This pin is decoupled with a low ESR 1F capacitor to pin SW. The voltage on the decoupling capacitor is refreshed through a rectifier from either VCC or an external source. Exposed Package Backside (SGND) (Pin 17): Low Noise Ground Reference. SGND connection is made through the exposed lead frame on back of TSSOP package which must be soldered to the PCB ground. 6 U U U 3800fb LT3800 FU CTIO AL DIAGRA VIN UVLO (<4V) VIN 1 8V REG 3.8V REG VCC UVLO (<6V) INTERNAL SUPPLY RAIL BST UVLO BOOSTED SWITCH DRIVER 15 TG 16 BOOST - + SHDN 3 BURST_EN 5 VFB 6 - ERROR AMP VC 7 gm + 0.5V CURRENT SENSE COMPARATOR 1V 1.185V 2A CSS 4 - 9 SENSE+ SENSE- + GND 17 + SOFT-START DISABLE/BURST ENABLE - + + + - - - W DRIVE CONTROL FEEDBACK REFERENCE 1.231V NOL SWITCH DRIVE LOGIC CONTROL 14 SW 12 VCC SYNCHRONOUS SWITCH DRIVER 11 BG DRIVE CONTROL 10 PGND OSCILLATOR Q S R SLOPE COMP GENERATOR Q R S + - U U - + REVERSE CURRENT INHIBIT - Burst Mode OPERATION 160mV + 10mV 8 3800 FD 3800fb 7 LT3800 APPLICATIO S I FOR ATIO Overview The LT3800 is a high input voltage range step-down synchronous DC/DC converter controller IC that uses a 200kHz constant frequency, current mode architecture with external N-channel MOSFET switches. The LT3800 has provisions for high efficiency, low load operation for battery-powered applications. Burst Mode operation reduces total average input quiescent currents to 100A during no load conditions. A low current shutdown mode can also be activated, reducing quiescent current to <10A. Burst Mode operation can be disabled if desired. The LT3800 also employs a reverse-current inhibit feature, allowing increased efficiencies during light loads through nonsynchronous operation. This feature disables the synchronous switch if inductor current approaches zero. If full time synchronous operation is desired, this feature can be disabled. Much of the LT3800's internal circuitry is biased from an internal linear regulator. The output of this regulator is the VCC pin, allowing bypassing of the internal regulator. The associated internal circuitry can be powered from the output of the converter, increasing overall converter efficiency. Using externally derived power also eliminates the IC's power dissipation associated with the internal VIN to VCC regulator. Theory of Operation (See Block Diagram) The LT3800 senses converter output voltage via the VFB pin. The difference between the voltage on this pin and an internal 1.231V reference is amplified to generate an error voltage on the VC pin which is, in turn, used as a threshold for the current sense comparator. During normal operation, the LT3800 internal oscillator runs at 200kHz. At the beginning of each oscillator cycle, the switch drive is enabled. The switch drive stays enabled until the sensed switch current exceeds the VC derived threshold for the current sense comparator and, in turn, disables the switch driver. If the current comparator 8 U threshold is not obtained for the entire oscillator cycle, the switch driver is disabled at the end of the cycle for 450ns. This minimum off-time mode of operation assures regeneration of the BOOST bootstrapped supply. Power Requirements The LT3800 is biased using a local linear regulator to generate internal operational voltages from the VIN pin. Virtually all of the circuitry in the LT3800 is biased via an internal linear regulator output (VCC). This pin is decoupled with a low ESR 1F capacitor to PGND. The VCC regulator generates an 8V output provided there is ample voltage on the VIN pin. The VCC regulator has approximately 1V of dropout, and will follow the VIN pin with voltages below the dropout threshold. The LT3800 has a start-up requirement of VIN > 7.5V. This assures that the onboard regulator has ample headroom to bring the VCC pin above its UVLO threshold. The VCC regulator can only source current, so forcing the VCC pin above its 8V regulated voltage allows use of externally derived power for the IC, minimizing power dissipation in the IC. Using the onboard regulator for start-up, then deriving power for VCC from the converter output maximizes conversion efficiencies and is common practice. If VCC is maintained above 6.5V using an external source, the LT3800 can continue to operate with VIN as low as 4V. The LT3800 operates with 3mA quiescent current from the VCC supply. This current is a fraction of the actual VCC quiescent currents during normal operation. Additional current is produced from the MOSFET switching currents for both the boosted and synchronous switches and are typically derived from the VCC supply. Because the LT3800 uses a linear regulator to generate VCC, power dissipation can become a concern with high VIN voltages. Gate drive currents are typically in the range of 5mA to 15mA per MOSFET, so gate drive currents can create substantial power dissipation. It is advisable to derive VCC and VBOOST power from an external source whenever possible. 3800fb W U U LT3800 APPLICATIO S I FOR ATIO The onboard VCC regulator will provide gate drive power for start-up under all conditions with total MOSFET gate charge loads up to 180nC. The regulator can operate the LT3800 continuously, provided the VIN voltage and/or MOSFET gate charge currents do not create excessive power dissipation in the IC. Safe operating conditions for continuous regulator use are shown in Figure 1. In applications where these conditions are exceeded, VCC must be derived from an external source after start-up. 70 60 50 VIN (V) 40 30 20 10 0 50 100 150 TOTAL FET GATE CHARGE (nC) 200 3800 F01 SAFE OPERATING CONDITIONS Figure 1. VCC Regulator Continuous Operating Conditions In LT3800 converter applications with output voltages in the 9V to 20V range, back-feeding VCC and VBOOST from the converter output is trivial, accomplished by connecting diodes from the output to these supply pins. Deriving these supplies from output voltages greater than 20V will require additional regulation to reduce the feedback voltage. Outputs lower than 9V will require step-up techniques to increase the feedback voltage to something greater than the 8V VCC regulated output. Low power boost switchers are sometimes used to provide the step-up function, but a simple charge-pump can perform this function in many instances. U Charge Pump Doubler VOUT B0520 VCC 1F LT3800 Si1555DL 1F B0520 BG W UU Charge Pump Tripler VOUT B0520 B0520 1F B0520 VCC 1F LT3800 1F Si1555DL Si1555DL 3800 AI01 BG Inductor Auxiliary Winding TG SW LT3800 VCC * N VOUT * BG 3800 AI04 3800fb 9 LT3800 APPLICATIO S I FOR ATIO Burst Mode The LT3800 employs low current Burst Mode functionality to maximize efficiency during no load and low load conditions. Burst Mode operation is enabled by shorting the BURST_EN pin to SGND. Burst Mode operation can be disabled by shorting BURST_EN to either VFB or VCC. When the required switch current, sensed via the VC pin voltage, is below 15% of maximum, the Burst Mode operation is employed and that level of sense current is latched onto the IC control path. If the output load requires less than this latched current level, the converter will overdrive the output slightly during each switch cycle. This overdrive condition is sensed internally and forces the voltage on the VC pin to continue to drop. When the voltage on VC drops 150mV below the 15% load level, switching is disabled and the LT3800 shuts down most of its internal circuitry, reducing total quiescent current to 100A. When the converter output begins to fall, the VC pin voltage begins to climb. When the voltage on the VC pin climbs back to the 15% load level, the IC returns to normal operation and switching resumes. An internal clamp on the VC pin is set at 100mV below the switch disable threshold, which limits the negative excursion of the pin voltage, minimizing the converter output ripple during Burst Mode operation. PULSE SKIP MODE IL DECREASING LOAD CURRENT Figure 2. Inductor Current vs Mode 10 U During Burst Mode operation, VIN pin current is 20A and VCC current is reduced to 80A. If no external drive is provided for VCC, all VCC bias currents originate from the VIN pin, giving a total VIN current of 100A. Burst current can be reduced further when VCC is driven using an output derived source, as the VCC component of VIN current is then reduced by the converter buck ratio. Reverse-Current Inhibit The LT3800 contains a reverse-current inhibit feature to maximize efficiency during light load conditions. This mode of operation allows discontinuous operation, and is sometimes referred to as "pulse-skipping" mode. Refer to Figure 2. This feature is enabled with Burst Mode operation, and can also be enabled while Burst Mode operation is disabled by shorting the BURST_EN pin to VFB. When reverse-current inhibit is enabled, the LT3800 sense amplifier detects inductor currents approaching zero and disables the synchronous switch for the remainder of the switch cycle. If the inductor current is allowed to go negative before the synchronous switch is disabled, the switch node could inductively kick positive with a high dv/dt. The LT3800 prevents this by incorporating a 10mV positive offset at the sense inputs. IL FORCED CONTINUOUS 3800 F02 W UU 3800fb LT3800 APPLICATIO S I FOR ATIO With the reverse-current inhibit feature enabled, an LT3800 converter will operate much like a nonsynchronous converter during light loads. Reverse-current inhibit reduces resistive losses associated with inductor ripple currents, which improves operating efficiencies during light-load conditions. An LT3800 DC/DC converter that is operating in reverseinhibit mode has a minimum load requirement of 1mA (BURST_EN = VFB). Since most applications use outputgenerated power for the LT3800, this requirement is met by the bias currents of the IC, however, for applications that do not derive power from the output, this requirement is easily accomplished by using a 1.2k resistor connected from VFB to ground as one of the converter output voltage programming resistors (R1). There are no minimum load restrictions when in Burst Mode operation (BURST_EN < 0.5V) or continuous conduction mode (BURST_EN > 2.5V). Soft-Start The LT3800 incorporates a programmable soft-start function to control start-up surge currents, limit output overshoot and for use in supply sequencing. The soft-start function directly monitors and controls output voltage slew rate during converter start-up. As the output voltage of the converter rises, the soft-start circuit monitors V/t current through a coupling capacitor and adjusts the voltage on the VC pin to maintain an average value of 2A. The soft-start function forces the programmed slew rate while the converter output rises to 95% regulation, which corresponds to 1.185V on the VFB pin. Once 95% regulation is achieved, the soft-start circuit is disabled. The soft-start circuit will re-enable when the VFB pin drops below 70% regulation, which corresponds to 300mV of control hysteresis on the VFB pin, which allows for a controlled recovery from a `brown-out' condition. The desired soft-start rise time (tSS) is programmed via a programming capacitor CSS1, using a value that U corresponds to 2A average current during the soft-start interval. This capacitor value follows the relation: CSS1 = 2E -6 * tSS VOUT W UU RSS is typically set to 200k for most applications. CSS1 VOUT A RSS CSS LT3800 3800 AI06 Considerations for Low Voltage Output Applications The LT3800 CSS pin biases to 220mV during the soft-start cycle, and this voltage is increased at network node "A" by the 2A signal current through RSS, so the output has to reach this value before the soft-start function is engaged. The value of this output soft-start start-up voltage offset (VOUT(SS)) follows the relation: VOUT(SS) = 220mV + RSS * 2E-6 which is typically 0.64V for RSS = 200k. In some low voltage output applications, it may be desirable to reduce the value of this soft-start start-up voltage offset. This is possible by reducing the value of RSS. With reduced values of RSS, the signal component caused by voltage ripple on the output must be minimized for proper soft-start operation. Peak-to-peak output voltage ripple (VOUT) will be imposed on node "A" through the capacitor CSS1. The value of RSS can be set using the following equation: RSS = VOUT 1.3E -6 It is important to use low ESR output capacitors for LT3800 voltage converter designs to minimize this ripple voltage component. A design with an excessive ripple component can be evidenced by observing the VC pin during the start cycle. 3800fb 11 LT3800 APPLICATIO S I FOR ATIO Soft-Start Characteristic Showing Excessive Ripple Component 250s/DIV 3800 AI07 The soft-start cycle should be evaluated to verify that the reduced RSS value allows operation without excessive modulation of the VC pin before finalizing the design. If the VC pin has an excessive ripple component during the soft-start cycle, converter output ripple should be reduced or RSS increased. Reduction in converter output ripple is typically accomplished by increasing output capacitance and/or reducing output capacitor ESR. External Current Limit Foldback Circuit An additional start-up voltage offset can occur during the period before the LT3800 soft-start circuit becomes active. Before the soft-start circuit throttles back the VC pin in response to the rising output voltage, current as high as the peak programmed current limit (IMAX) can flow in the inductor. Switching will stop once the soft-start circuit takes hold and reduces the voltage on the VC pin, but the output voltage will continue to increase as the stored energy in the inductor is transferred to the output capacitor. With IMAX flowing in the inductor, the resulting leading-edge rise on VOUT due to energy stored in the inductor follows the relationship: VOUT L = IMAX * COUT 1/ 2 12 U Desirable Soft-Start Characteristic VOUT VOUT VOUT(SS) V(VC) VOUT(SS) V(VC) 250s/DIV 3800 AI08 W UU Inductor current typically doesn't reach IMAX in the few cycles that occur before soft-start becomes active, but can with high input voltages or small inductors, so the above relation is useful as a worst-case scenario. This energy transfer increase in output voltage is typically small, but for some low voltage applications with relatively small output capacitors, it can become significant. The voltage rise can be reduced by increasing output capacitance, which puts additional limitations on COUT for these low voltage supplies. Another approach is to add an external current limit foldback circuit which reduces the value of IMAX during start-up. An external current limit foldback circuit can be easily incorporated into an LT3800 DC/DC converter application by placing a 1N4148 diode and a 47k resistor from the converter output (VOUT) to the LT3800's VC pin. This limits the peak current to 0.25 * IMAX when VOUT = 0V. A current limit foldback circuit also has the added advantage of providing a reduced output current in the DC/DC converter during short-circuit fault conditions, so a foldback circuit may be useful even if the soft-start function is disabled. If the soft-start circuit is disabled by shorting the CSS pin to ground, the external current limit fold-back circuit must be modified by adding an additional diode and resistor. The 2-diode, 2-resistor network shown also provides 0.25 * IMAX when VOUT = 0V. 3800fb LT3800 APPLICATIO S I FOR ATIO Current Limit Foldback Circuit for Applications That Use Soft-Start VC 1N4148 47k VOUT 3800 AI09 Adaptive Nonoverlap (NOL) Output Stage The FET driver output stages implement adaptive nonoverlap control. This feature maintains a constant dead time, preventing shoot-through switch currents, independent of the type, size or operating conditions of the external switch elements. Each of the two switch drivers contains a NOL control circuit, which monitors the output gate drive signal of the other switch driver. The NOL control circuits interrupt the "turn on" command to their associated switch driver until the other switch gate is fully discharged. Antislope Compensation Most current mode switching controllers use slope compensation to prevent current mode instability. The LT3800 is no exception. A slope-compensation circuit imposes an artificial ramp on the sensed current to increase the rising slope as duty cycle increases. Unfortunately, this additional ramp corrupts the sensed current value, reducing the achievable current limit value by the same amount as the added ramp represents. As such, current limit is typically reduced as duty cycles increase. The LT3800 contains circuitry to eliminate the current limit reduction typically associated with slope compensation. As the slope-compensation ramp is added to the sensed current, a similar ramp is added to the current limit threshold reference. The end result is that current limit is not compromised, so a LT3800 converter can provide full power regardless of required duty cycle. U Alternative Current Limit Foldback Circuit for Applications That Have Soft-Start Disabled VC 1N4148 1N4148 39k 27k 3800 AI10 W UU VOUT Shutdown The LT3800 SHDN pin uses a bandgap generated reference threshold of 1.35V. This precision threshold allows use of the SHDN pin for both logic-level controlled applications and analog monitoring applications such as power supply sequencing. The LT3800 operational status is primarily controlled by a UVLO circuit on the VCC regulator pin. When the IC is enabled via the SHDN pin, only the VCC regulator is enabled. Switching remains disabled until the UVLO threshold is achieved at the VCC pin, when the remainder of the IC is enabled and switching commences. Because an LT3800 controlled converter is a power transfer device, a voltage that is lower than expected on the input supply could require currents that exceed the sourcing capabilities of that supply, causing the system to lock up in an undervoltage state. Input supply start-up protection can be achieved by enabling the SHDN pin using a resistive divider from the VIN supply to ground. Setting the divider output to 1.35V when that supply is at an adequate voltage prevents an LT3800 converter from drawing large currents until the input supply is able to provide the required power. 120mV of input hysteresis on the SHDN pin allows for almost 10% of input supply droop before disabling the converter. 3800fb 13 LT3800 APPLICATIO S I FOR ATIO Programming LT3800 VIN UVLO VIN RB 3 LT3800 SHDN RA SGND 17 3800 AI02 The UVLO voltage, VIN(UVLO), is set using the following relation: VIN(UVLO) - 1.35V RA = RB * 1.35V If additional hysteresis is desired for the enable function, an external positive feedback resistor can be used from the LT3800 regulator output. The shutdown function can be disabled by connecting the SHDN pin to VIN through a large value pull-up resistor. This pin contains a low impedance clamp at 6V, so the SHDN pin will sink current from the pull-up resistor (RPU): V - 6V ISHDN = IN RPU Because this arrangement will pull the SHDN pin to the 6V clamp voltage, it will violate the 5V absolute maximum voltage rating of the pin. This is permitted, however, as long as the absolute maximum input current rating of 1mA is not exceeded. Input SHDN pin currents of <100A are recommended; a 1M or greater pull-up resistor is typically used for this configuration. 14 U Inductor Selection The primary criterion for inductor value selection in LT3800 applications is ripple current created in that inductor. Basic design considerations for ripple current are output voltage ripple, and the ability of the internal slope compensation waveform to prevent current mode instability. Once the value is determined, an inductor must also have a saturation current equal to or exceeding the maximum peak current in the inductor. Ripple current (IL) in an inductor for a given value (L) can be approximated using the relation: V V IL = 1- OUT * OUT VIN fO * L W UU The typical range of values for I is 20% to 40% of IOUT(MAX), where IOUT(MAX) is the maximum converter output load current. Ripple currents in this range typically yield a good design compromise between inductor performance versus inductor size and cost, and values in this range are generally a good starting point. A starting point inductor value can thus be determined using the relation: VOUT 1- VIN L = VOUT * fO * 0.3 * IOUT(MAX) Use of smaller inductors increase output ripple currents, requiring more capacitance on the converter output. Also, with converter operation with duty cycles greater than 50%, the slope compensation criterion, described later, must be met. Designing for smaller ripple currents requires larger inductor values, which can increase converter cost and/or footprint. 3800fb LT3800 APPLICATIO S I FOR ATIO Some magnetics vendors specify a volt-second product in their data sheet. If they do not, consult the vendor to make sure the specification is not being exceeded by your design. The required volt-second product is calculated as follows: Volt - Second VOUT fO V * 1 - OUT VIN Magnetics vendors specify either the saturation current, the RMS current, or both. When selecting an inductor based on inductor saturation current, the peak current through the inductor, IOUT(MAX) + (I/2), is used. When selecting an inductor based on RMS current the maximum load current, IOUT(MAX), is used. The requirement for avoiding current mode instability is keeping the rising slope of sensed inductor ripple current (S1) greater than the falling slope (S2). During continuouscurrent switcher operation, the rising slope of the current waveform in the switched inductor is less than the falling slope when operating at duty cycles (DC) greater than 50%. To avoid the instability condition during this operation, a false signal is added to the sensed current, increasing the perceived rising slope. To prevent current mode instability, the slope of this false signal (Sx) must be sufficient such that the sensed rising slope exceeds the falling slope, or S1 + Sx S2. This leads to the following relations: Sx S2 (2DC - 1)/DC where: S2 ~ VOUT/L Solving for L yields a relation for the minimum inductance that will satisfy slope compensation requirements: 2DC - 1 LMIN = VOUT * DC * Sx The LT3800 maximizes available dynamic range using a slope compensation generator that continuously increases the additional signal slope as duty cycle increases. The slope compensation waveform is calibrated at an 80% U duty cycle, to generate an equivalent slope of at least 1E5 * ILIMIT A/sec, where ILIMIT is the programmed converter current limit. Current limit is programmed by using a sense resistor (RS) such that ILIMIT = 150mV/RS, so the equation for the minimum inductance to meet the current mode instability criterion can be reduced to: LMIN = (5E-5)(VOUT)(RS) For example, with VOUT = 5V and RS = 20m: LMIN = (5E-5)(5)(0.02) = 5H After calculating the minimum inductance value, the voltsecond product, the saturation current and the RMS current for your design, an off the shelf inductor can be selected from a magnetics vendor. A list of magnetics vendors can be found at http://www.linear.com/ezone/ vlinks or by contacting the Linear Technology Applications department. Output Voltage Programming Output voltage is programmed through a resistor feedback network to VFB (Pin 6) on the LT3800. This pin is the inverting input of the error amplifier, which is internally referenced to 1.231V. The divider is ratioed to provide 1.231V at the VFB pin when the output is at its desired value. The output voltage is thus set following the relation: V R2 = R1 * OUT - 1 1.231 when an external resistor divider is connected to the output as shown. Programming LT3800 Output Voltage VOUT LT3800 VFB 6 R2 R1 SGND 17 3800 AI03 W UU 3800fb 15 LT3800 APPLICATIO S I FOR ATIO Power MOSFET Selection External N-channel MOSFET switches are used with the LT3800. The positive gate-source drive voltage of the LT3800 for both switches is roughly equivalent to the VCC supply voltage, for use of standard threshold MOSFETs. Selection criteria for the power MOSFETs include the "ON" resistance (RDS(ON)), total gate charge (QG), reverse transfer capacitance (CRSS), maximum drain-source voltage (VDSS) and maximum current. The power FETs selected must have a maximum operating VDSS exceeding the maximum VIN. VGS voltage maximum must exceed the VCC supply voltage. Total gate charge (QG) is used to determine the FET gate drive currents required. QG increases with applied gate voltage, so the QG for the maximum applied gate voltage must be used. A graph of QG vs. VGS is typically provided in MOSFET datasheets. In a configuration where the LT3800 linear regulator is providing VCC and VBOOST currents, the VCC 8V output voltage can be used to determine QG. Required drive current for a given FET follows the simple relation: IGATE = QG(8V) * fO QG(8V) is the total FET gate charge for VGS = 8V, and f0 = operating frequency. If these currents are externally derived by backdriving VCC, use the backfeed voltage to determine QG. Be aware, however, that even in a backfeed configuration, the drive currents for both boosted and synchronous FETs are still typically supplied by the LT3800 internal VCC regulator during start-up. The LT3800 can start using FETs with a combined QG(8V) up to 180nC. Once voltage requirements have been determined, RDS(ON) can be selected based on allowable power dissipation and required output current. In an LT3800 buck converter, the average inductor current is equal to the DC load current. The average currents through the main (bootstrapped) and synchronous (ground-referred) switches are: 16 U IMAIN = (ILOAD)(DC) ISYNC = (ILOAD)(1 - DC) The RDS(ON) required for a given conduction loss can be calculated using the relation: PLOSS = ISWITCH2 * RDS(ON) In high voltage applications (VIN > 20V), the main switch is required to slew very large voltages. MOSFET transition losses are proportional to VIN2 and can become the dominant power loss term in the main switch. This transition loss takes the form: PTR (k)(VIN)2(ISWITCH)(CRSS)(fO) where k is a constant inversely related to the gate drive current, approximated by k = 2 in LT3800 applications, and ISWITCH is the converter output current. The power loss terms for the switches are thus: PMAIN = (DC)(ISWITCH)2(1 + d)(RDS(ON)) + 2(VIN)2(ISWITCH)(CRSS)(fO) PSYNC = (1 - DC)(ISWITCH)2(1 + d)(RDS(ON)) The (1 + d) term in the above relations is the temperature dependency of RDS(ON), typically given in the form of a normalized RDS(ON) vs Temperature curve in a MOSFET data sheet. The CRSS term is typically smaller for higher voltage FETs, and it is often advantageous to use a FET with a higher VDS rating to minimize transition losses at the expense of additional RDS(ON) losses. In some applications, parasitic FET capacitances couple the negative going switch node transient onto the bottom gate drive pin of the LT3800, causing a negative voltage in excess of the Absolute Maximum Rating to be imposed on that pin. Connection of a catch Schottky diode from this pin to ground will eliminate this effect. A 1A current rating is typically sufficient for the diode. 3800fb W UU LT3800 APPLICATIO S I FOR ATIO Input Capacitor Selection The large currents typical of LT3800 applications require special consideration for the converter input and output supply decoupling capacitors. Under normal steady state buck operation, the source current of the main switch MOSFET is a square wave of duty cycle VOUT/VIN. Most of this current is provided by the input bypass capacitor. To prevent large input voltage transients and avoid bypass capacitor heating, a low ESR input capacitor sized for the maximum RMS current must be used. This maximum capacitor RMS current follows the relation: IRMS = I MAX ( VOUT ( VIN - VOUT )) VIN 1 2 which peaks at a 50% duty cycle, when IRMS = IMAX/2. The bulk capacitance is calculated based on an acceptable maximum input ripple voltage, VIN, which follows the relation: VOUT VIN CIN(BULK) = IOUT(MAX) * VIN * fO V is typically on the order of 100mV to 200mV. Aluminum electrolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. The capacitor voltage rating must be rated greater than VIN(MAX). The combination of aluminum electrolytic capacitors and ceramic capacitors is a common approach to meeting supply input capacitor requirements. Multiple capacitors are also commonly paralleled to meet size or height requirements in a design. Capacitor ripple current ratings are often based on only 2000 hours (three months) lifetime; it is advisable to derate either the ESR or temperature rating of the capacitor for increased MTBF of the regulator. U Output Capacitor Selection The output capacitor in a buck converter generally has much less ripple current than the input capacitor. Peak-topeak ripple current is equal to that in the inductor (IL), typically a fraction of the load current. COUT is selected to reduce output voltage ripple to a desirable value given an expected output ripple current. Output ripple (VOUT) is approximated by: VOUT IL(ESR + [(8)(fO) * COUT]-1) where fO = operating frequency. VOUT increases with input voltage, so the maximum operating input voltage should be used for worst-case calculations. Multiple capacitors are often paralleled to meet ESR requirements. Typically, once the ESR requirement is satisfied, the capacitance is adequate for filtering and has the required RMS current rating. An additional ceramic capacitor in parallel is commonly used to reduce the effect of parasitic inductance in the output capacitor, which reduces high frequency switching noise on the converter output. Increasing inductance is an option to reduce ESR requirements. For extremely low VOUT, an additional LC filter stage can be added to the output of the supply. Application Note 44 has information on sizing an additional output LC filter. Layout Considerations The LT3800 is typically used in DC/DC converter designs that involve substantial switching transients. The switch drivers on the IC are designed to drive large capacitances and, as such, generate significant transient currents themselves. Careful consideration must be made regarding supply bypass capacitor locations to avoid corrupting the ground reference used by IC. Typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from SGND, to which sensitive circuits such as the error amp reference and the current sense circuits are referred. 3800fb W UU 17 LT3800 APPLICATIO S I FOR ATIO Effective grounding can be achieved by considering switch current in the ground plane, and the return current paths of each respective bypass capacitor. The VIN bypass return, VCC bypass return, and the source of the synchronous FET carry PGND currents. SGND originates at the negative terminal of the VOUT bypass capacitor, and is the small signal reference for the LT3800. Don't be tempted to run small traces to separate ground paths. A good ground plane is important as always, but PGND referred bypass elements must be oriented such that transient currents in these return paths do not corrupt the SGND reference. During the dead-time between switch conduction, the body diode of the synchronous FET conducts inductor current. Commutating this diode requires a significant charge contribution from the main switch. At the instant the body diode commutates, a current discontinuity is created and parasitic inductance causes the switch node to fly up in response to this discontinuity. High currents and excessive parasitic inductance can generate extremely fast dV/dt rise times. This phenomenon can cause avalanche breakdown in the synchronous FET body diode, significant inductive overshoot on the switch node, and shoot-through currents via parasitic turn-on of the synchronous FET. Layout practices and component orientations that minimize parasitic inductance on this node is critical for reducing these effects. Ringing waveforms in a converter circuit can lead to device failure, excessive EMI, or instability. In many cases, you can damp a ringing waveform with a series RC network across the offending device. In LT3800 applications, any ringing will typically occur on the switch node, which can usually be reduced by placing a snubber across the synchronous FET. Use of a snubber network, however, should be considered a last resort. Effective layout practices typically reduce ringing and overshoot, and will eliminate the need for such solutions. Effective grounding techniques are critical for successful DC/DC converter layouts. Orient power path components 18 U such that current paths in the ground plane do not cross through signal ground areas. Signal ground refers to the Exposed Pad on the backside of the LT3800 IC. SGND is referenced to the (-) terminal of the VOUT decoupling capacitor and is used as the converter voltage feedback reference. Power ground currents are controlled on the LT3800 via the PGND pin, and this ground references the high current synchronous switch drive components, as well as the local VCC supply. It is important to keep PGND and SGND voltages consistent with each other, so separating these grounds with thin traces is not recommended. When the synchronous FET is turned on, gate drive surge currents return to the LT3800 PGND pin from the FET source. The BOOST supply refresh surge currents also return through this same path. The synchronous FET must be oriented such that these PGND return currents do not corrupt the SGND reference. Problems caused by the PGND return path are generally recognized during heavy load conditions, and are typically evidenced as multiple switch pulses occurring during a single 5s switch cycle. This behavior indicates that SGND is being corrupted and grounding should be improved. SGND corruption can often be eliminated, however, by adding a small capacitor (100pF-200pF) across the synchronous switch FET from drain to source. The high di/dt loop formed by the switch MOSFETs and the input capacitor (CIN) should have short wide traces to minimize high frequency noise and voltage stress from inductive ringing. Surface mount components are preferred to reduce parasitic inductances from component leads. Connect the drain of the main switch MOSFET directly to the (+) plate of CIN, and connect the source of the synchronous switch MOSFET directly to the (-) terminal of CIN. This capacitor provides the AC current to the switch MOSFETs. Switch path currents can be controlled by orienting switch FETs, the switched inductor, and input and output decoupling capacitors in close proximity to each other. Locate the VCC and BOOST decoupling capacitors in close proximity to the IC. These capacitors carry the MOSFET 3800fb W UU LT3800 APPLICATIO S I FOR ATIO drivers' high peak currents. Locate the small-signal components away from high frequency switching nodes (BOOST, SW, TG, VCC and BG). Small-signal nodes are oriented on the left side of the LT3800, while high current switching nodes are oriented on the right side of the IC to simplify layout. This also helps prevent corruption of the SGND reference. Connect the VFB pin directly to the feedback resistors independent of any other nodes, such as the SENSE- pin. The feedback resistors should be connected between the (+) and (-) terminals of the output capacitor (COUT). Orientation of Components Isolates Power Path and PGND Currents, Preventing Corruption of SGND Reference VIN BOOST SW SGND REFERRED COMPONENTS LT3800 VCC SGND PGND VOUT + U Locate the feedback resistors in close proximity to the LT3800 to minimize the length of the high impedance VFB node. The SENSE- and SENSE+ traces should be routed together and kept as short as possible. The LT3800 packaging has been designed to efficiently remove heat from the IC via the Exposed Pad on the backside of the package. The Exposed Pad is soldered to a copper footprint on the PCB. This footprint should be made as large as possible to reduce the thermal resistance of the IC case to ambient air. + TG SW BG 3800 AI05 W UU ISENSE 3800fb 19 LT3800 TYPICAL APPLICATIO S 6.5V-55V to 5V 10A DC/DC Converter with Charge Pump Doubler VCC Refresh and Current Limit Foldback VIN 6.5V TO 55V + C8 56F 63V x2 VIN RA 1M C7 1.5nF NC LT3800 SHDN R4 75k CSS NC VCC BG PGND C3 1F 16V X7R SW BOOST TG C1 1F 16V X7R R1 100k 1% R2 309k 1% R3 62k C9 470pF C10 100pF D2 1N4148 R5 47k EFFICIENCY (%) 20 U C2 1F 100V X7R x3 D1 BAS19 M1 Si7850DP x2 L1 5.6H M2 Si7370DP x2 DS3 B160 x2 BURST_EN VFB VC SENSE- SENSE+ SGND RS 0.01 VOUT 5V AT 10A DS2 MBRO520L DS1 MBRO520L M3 1/2 Si1555DL M4 1/2 Si1555DL C6 10F 6.3V X7R + C5 220F x2 3800 TA02a C4 1F C5: SANYO POSCAP 6TP220M L1: IHLP-5050FD-01 Efficiency and Power Loss 100 95 90 85 80 75 70 0 2 4 6 IOUT (A) 8 10 3800 TA02b 12 VIN = 24V VIN = 48V POWER LOSS (W) VIN = 13.8V 10 8 VIN = 55V POWER LOSS VIN = 48V 6 4 POWER LOSS VIN = 13.8V 2 0 3800fb LT3800 TYPICAL APPLICATIO S 9V-38V to 3.3V 10A DC/DC Converter with Input UVLO and Burst Mode Operation No Load I(VIN) = 100A VIN 9V TO 38V + C8 100F 50V x2 RA RB 1M 187k C1 1nF R4 39k R1 100k 1% C10 100pF R2 169k 1% R3 82k C2 330pF C3 100pF EFFICIENCY (%) U VIN NC BOOST TG LT3800 SW NC VCC BG PGND C5 1F 16V X7R C9 4.7F 50V X7R x3 M1 Si7884DP SHDN CSS BURST_EN VFB VC D1 MBR520 C4 1F 16V X7R L1 3.3H DS1 SS14 x2 M2 Si7884DP SENSE- SENSE+ SGND RS 0.01 VOUT 3.3V AT 10A C6: SANYO POSCAP 4TPD470M L1: IHLP-5050FD-01 C7 10F 6.3V X7R + C6 470F x2 3800 TA03a Efficiency and Power Loss 92 90 88 86 84 82 80 78 0.1 VIN = 13.8V 7 6 5 4 3 2 1 0 10 3800 TA03b POWER LOSS (W) 1 ILOAD (A) 3800fb 21 LT3800 TYPICAL APPLICATIO S 9V-38V to 5V 6A DC/DC Converter with All Ceramic Capacitors, Input UVLO, Burst Mode Operation and Current Limit Foldback VIN 9V TO 38V C8 22F x3 C9 1nF RB 187k RA 1M C1 3.9nF R1 49.9k 1% R2 154k 1% C6 47pF R5 D2 1N4148 47k R3 27k C2 1nF C3 100pF EFFICIENCY (%) 22 U VIN NC BOOST TG LT3800 SW NC VCC BG PGND C5 1F 10V X7R M1 Si7884DP SHDN R4 51k CSS BURST_EN VFB VC D1 BAS19 C4 1F 10V X7R L1 10H M2 Si7884DP DS1 SS14 SENSE- SENSE+ SGND RS 0.02 VOUT 5V AT 6A 3800 TA05a C7: TDK C4532X5R0J107MT C8: TDK C5750X7R1E226MT L1: IHLP-5050FD-01 C7 100F x2 Efficiency and Power Loss 100 95 90 85 80 75 70 65 60 0.001 0.01 0.1 ILOAD (A) 3800 TA05b VIN = 13.8V 3.20 2.80 2.40 POWER LOSS (W) 2.00 1.60 1.20 0.80 0.40 0 1 10 3800fb LT3800 PACKAGE DESCRIPTIO 3.58 (.141) 6.60 0.10 4.50 0.10 SEE NOTE 4 0.65 BSC RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50* (.169 - .177) 0.09 - 0.20 (.0035 - .0079) 0.50 - 0.75 (.020 - .030) NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U FE Package 16-Lead Plastic TSSOP (4.4mm) (Reference LTC DWG # 05-08-1663) Exposed Pad Variation BC 4.90 - 5.10* (.193 - .201) 3.58 (.141) 16 1514 13 12 1110 9 2.94 (.116) 0.45 0.05 1.05 0.10 6.40 2.94 (.252) (.116) BSC 12345678 1.10 (.0433) MAX 0 - 8 0.25 REF 0.65 (.0256) BSC 0.195 - 0.30 (.0077 - .0118) TYP 0.05 - 0.15 (.002 - .006) FE16 (BC) TSSOP 0204 4. RECOMMENDED MINIMUM PCB METAL SIZE FOR EXPOSED PAD ATTACHMENT *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.150mm (.006") PER SIDE 3800fb 23 LT3800 TYPICAL APPLICATIO VIN 24V TO 48V 24V-48V to -12V 75W Inverting DC/DC Converter with VIN UVLO + R7 1M R8 1M 2N3906 R3 1M R6 130k R2 174k 1% C9 56F 63V x2 C10 1F 100V X7R x4 VIN NC LT3800 C1 1nF SHDN R1 200k CSS BURST_EN VFB VC R4 39k C3 470pF C4 100pF L1: COEV MGPWL-00099 NC VCC BG PGND C6 1F 16V X7R SW BOOST TG C2 1F 16V X7R M1 FDD3570 L1 15H RS 0.01 R5 20k 1% EFFICIENCY (%) RELATED PARTS PART NUMBER LTC1735 LTC1778 LT 1934 LT1952 LT1976 LT3010 LT3430/LT3431 LTC3703 LTC3703-5 LTC3727-1 LTC3728L (R) DESCRIPTION Synchronous Step-Down Controller No RSENSETM Synchronous Step-Down Controller Micropower Step-Down Switching Regulator Synchronous Single Switch Forward Converter 60V Switching Regulator 3V to 80V LDO 3A, 60V Switching Regulators 100V Synchronous Step-Down Controller 60V Synchronous Step-Down Controller High VOUT 2-Phase Dual Step-Down Controller 2-Phase, Dual Synchronous Step-Down Controller No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. 3800fb 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com U D1 BAS19 D2 1N4148 M2 FDD3570 C7 150pF 100V DS1 B180 SENSE- SENSE+ SGND C8 4.7F 16V X7R + C5 270F 16V SPRAGUE SP VOUT -12V 3800 TA04a 75W Efficiency and Power Loss 100 90 VIN = 24V 80 70 60 VIN = 36V LOSS 50 40 0.1 1 ILOAD (A) 2 0 10 3800 TA04b 12 10 POWER LOSS (W) VIN = 48V VIN = 36V 8 6 4 COMMENTS 4V VIN 36V, 0.8V VOUT 6V, IOUT 20A Current Mode Without Using Sense Resistor, 4V VIN 36V 3.2V VIN 34V, 300mA Switch, ThinSOTTM Package 25W to 500W Isolated Power Supplies, Small Size, High Efficiency 3.2V VIN 60V, 1.5A Switch, 16-Lead TSSOP 50mA Output Current, 1.275V VOUT 60V 5.5V VIN 60V, 200kHz, 16-Lead TSSOP Large 1 Gate Drivers, No RSENSE Large 1 Gate Drivers, No RSENSE 0.8V VOUT 14V, PLL: 250kHz to 550kHz 550kHz, PLL: 250kHz to 550kHz, 4V VIN 36V LT 1007 REV B * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 2005 |
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